๋ณธ๋ฌธ์œผ๋กœ ๊ฑด๋„ˆ๋›ฐ๊ธฐ

SIC/XE Machine Architecture

์‹œ์Šคํ…œ ์†Œํ”„ํŠธ์›จ์–ด์™€ ๊ธฐ๊ณ„ ์ข…์†์„ฑ#

  1. ์‹œ์Šคํ…œ ์†Œํ”„ํŠธ์›จ์–ด์˜ ์„ค๊ณ„๋Š” ๊ทธ ์†Œํ”„ํŠธ์›จ์–ด๊ฐ€ ๋™์ž‘ํ•  ๋จธ์‹ ์˜ ๊ตฌ์กฐ์™€ ๋ฐ€์ ‘ํ•œ ๊ด€๋ จ์ด์žˆ๋‹ค.

    • ์˜ˆ๋ฅผ ๋“ค์–ด, ์–ด์…ˆ๋ธ”๋Ÿฌ๋Š” mnemonic instruction์„ machine code๋กœ ํ•ด์„ํ•˜๊ณ , ์šด์˜์ฒด์ œ๋Š” ์ปดํ“จํŒ… ์‹œ์Šคํ…œ์˜ ์ž์›์„ ์ง์ ‘์ ์œผ๋กœ ๊ด€๋ฆฌํ•œ๋‹ค.
  2. ์‹œ์Šคํ…œ์˜ ๊ตฌ์ฒด์ ์ธ ๊ตฌํ˜„๋ฒ•์€ ์‹œ๊ฐ„์ด ์ง€๋‚จ์— ๋”ฐ๋ผ ๋ณ€ํ–ˆ์ง€๋งŒ, ๋ฐ”ํƒ•์— ๊น”๋ ค์žˆ๋Š” ์ปจ์…‰์€ ์—ฌ์ „ํ•˜๋‹ค.

  3. ์‹œ์Šคํ…œ ์†Œํ”„ํŠธ์›จ์–ด์˜ ๊ธฐ๋ณธ์ ์ธ ๊ตฌ์กฐ์™€ ์„ค๊ณ„๋Š” ๋Œ€๋ถ€๋ถ„์˜ ์ปดํ“จํ„ฐ์—์„œ ๋น„์Šทํ•˜๋‹ค.

    • ์˜ˆ๋ฅผ ๋“ค์–ด, ์–ด์…ˆ๋ธ”๋Ÿฌ์˜ ์ผ๋ฐ˜์ ์ธ ์„ค๊ณ„์™€ ๋กœ์ง์€ ๋‹ค๋ฅธ ๋จธ์‹  ์•„ํ‚คํ…์ณ์—์„œ ๊ฑฐ์˜ ๋™์ผํ•˜๋‹ค.

SIC์™€ SIC/XE#

์‹ค์ œ ๋จธ์‹ ์€ ๋งค์šฐ ๋ณต์žกํ•˜์—ฌ ํ•™์Šตํ•˜๊ธฐ ์ข‹์ง€ ์•Š๊ณ , ๊ฐ€์žฅ ๊ธฐ๋ณธ์ ์ธ ๊ธฐ๋Šฅ์— ์ถฉ์‹คํ•  ์ˆ˜ ์—†์œผ๋ฏ€๋กœ, SIC์™€ SIC/XE๋ฅผ ํ†ตํ•ด ์ดํ•ดํ•˜๋„๋ก ํ•œ๋‹ค. SIC์™€ SIC/XE๋Š” ๊ฐ€์ƒ์˜ ์ปดํ“จํ„ฐ (hypothetical computer)๋กœ ์‹ค์ œ ๋จธ์‹ ์—์„œ ๋ณผ ์ˆ˜ ์žˆ๋Š” ํ•˜๋“œ์›จ์–ด์˜ ๊ธฐ๋Šฅ๋“ค์„ ํฌํ•จํ•˜๊ณ , ์ผ๋ฐ˜์ ์ด์ง€ ์•Š๊ณ  ๊ด€๋ จ ์—†๋Š” ๋ณต์žก์„ฑ๋“ค์€ ์ œ๊ฑฐํ–ˆ๋‹ค.

๊ตฌ์ฒด์ ์ธ ์„ธ๋ถ€์‚ฌํ•ญ์œผ๋กœ๋ถ€ํ„ฐ ๋–จ์–ด์ ธ์„œ ์‹œ์Šคํ…œ ์†Œํ”„ํŠธ์›จ์–ด์˜ ๊ธฐ๋ณธ์ ์ธ ์ปจ์…‰์„ ์ดํ•ดํ•˜๋„๋ก ํ•œ๋‹ค.

SIC๋Š” Simplified Instructional Computer๋กœ ๊ฐ€์ƒ ์ปดํ“จํ„ฐ์˜ ํ‘œ์ค€์ ์ธ ๋ชจ๋ธ์ด๊ณ , SIC/XE๋Š” SIC์˜ ํ™•์žฅ๋œ ๋ฒ„์ „(the eXtra Equipment(or Expensive))์ด๋‹ค. SIC์—์„œ ์ž‘๋™ํ•˜๋Š” ํ”„๋กœ๊ทธ๋žจ์€ ๋ชจ๋‘ SIC/XE์—์„œ ์ •์ƒ์ ์œผ๋กœ ๋™์ž‘ํ•˜๋Š” ์ƒ์œ„ํ˜ธํ™˜(upward compatibility)์„ ๋ณด์žฅํ•œ๋‹ค. ํ•˜์ง€๋งŒ SIC/XE์—์„œ ์ž‘๋™ํ•˜๋Š” ํ”„๋กœ๊ทธ๋žจ์ด SIC์—์„œ ์ž‘๋™๋œ๋‹ค๋Š” ํ•˜์œ„ํ˜ธํ™˜(backward compatibility)์€ ๋ณด์žฅํ•˜์ง€ ์•Š๋Š”๋‹ค.


SIC Machine Architecture#

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๋ฉ”๋ชจ๋ฆฌ#

  • 8๋น„ํŠธ ๋ฐ”์ดํŠธ๋กœ ๊ตฌ์„ฑ

  • 3๋ฐ”์ดํŠธ ์›Œ๋“œ(Word)๋กœ ๊ตฌ์„ฑ(24๋น„ํŠธ)

  • ์ „์ฒด ๋ฉ”๋ชจ๋ฆฌ๋Š” 32KB(2^15 ๋ฐ”์ดํŠธ)

๋ ˆ์ง€์Šคํ„ฐ#

SIC์—๋Š” ํŠน์ˆ˜ํ•œ ๋ชฉ์ ์„ ๊ฐ€์ง„ 5๊ฐœ์˜ ๋ ˆ์ง€์Šคํ„ฐ๊ฐ€ ์กด์žฌํ•œ๋‹ค. ๊ธธ์ด๋Š” ๊ฐ๊ฐ 24๋น„ํŠธ์ด๊ณ  ์ˆซ์ž ํ‘œํ˜„๊ณผ Mnemonic ํ‘œํ˜„์„ ๊ฐ€์ง„๋‹ค.

  • A(0) : Accumulator register

  • X(1) : Index register

  • L(2) : Linkage register

  • PC(8) : Program Counter register

  • SW(9) : Status Word register

๋ฐ์ดํ„ฐ ํฌ๋งท#

Integer์™€ Character ๋‘ ๊ฐ€์ง€ ๋ฐ์ดํ„ฐ ํฌ๋งท์„ ์ง€์›ํ•œ๋‹ค. (Floating-point๋Š” ์ง€์›ํ•˜์ง€์•Š์Œ)

Character๋Š” 8๋น„ํŠธ(ASCII), Integer๋Š” 24๋น„ํŠธ

๋ช…๋ น์–ด ํฌ๋งท(Instruction format)#

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  • opcode(8๋น„ํŠธ) : ๋ช…๋ น์–ด๋ฅผ ๊ตฌ๋ถ„ํ•˜๊ธฐ ์œ„ํ•œ ๋ถ€๋ถ„

  • X(1๋น„ํŠธ) : Indexed addressing or Direct addressing ์ธ์ง€๋ฅผ ๋‚˜ํƒ€๋‚ด๋Š” ํ”Œ๋ž˜๊ทธ.

  • address(15๋น„ํŠธ) : ์ฃผ์†Œ๋ฅผ ๋‚˜ํƒ€๋‚ด๋Š” ๋ถ€๋ถ„

Addressing Modes#

  • Direct addressing mode (x=0) : Target Address = address

  • Indexed addressing mode (x=1) : Target Address = address + (X)

์ง์ ‘ ์ฃผ์†Œ๋Š” ์ฃผ์†Œ๋ฅผ ์ง์ ‘ ์‚ฌ์šฉํ•˜๊ณ  ์ธ๋ฑ์Šค ์ฃผ์†Œ๋Š” ํ•ด๋‹น ์ฃผ์†Œ์— Index ๋ ˆ์ง€์Šคํ„ฐ์˜ ๊ฐ’์„๋”ํ•œ ๊ฒƒ์„ ์ฃผ์†Œ๋กœ ์‚ฌ์šฉํ•œ๋‹ค.

๋ช…๋ น์–ด ์ข…๋ฅ˜(Instruction Type)#

  • Load & Store

  • Arithmetic & Logic

  • Comparison

  • Conditional Jumps

  • Subroutine Linkage

  • I/O


๋ช…๋ น์–ด ํ‘œ๊ธฐ๋ฒ•

A โ† (A) + (m .. m+2) : A ๋ ˆ์ง€์Šคํ„ฐ์— A ๋ ˆ์ง€์Šคํ„ฐ์˜ ๊ฐ’๊ณผ ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ m, m+1, m+2 ์— ์žˆ๋Š” ๊ฐ’(3Bytes word ์ด๋ฏ€๋กœ)์„ ๋”ํ•ด์„œ ๋„ฃ๋Š”๋‹ค.

() ๋กœ ๊ฐ์‹ธ ์žˆ์œผ๋ฉด ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ ๋˜๋Š” ๋ ˆ์ง€์Šคํ„ฐ ์ฃผ์†Œ์— ๋‹ด๊ฒจ์žˆ๋Š” ๊ฐ’์„ ๋งํ•˜๊ณ  ๊ฐ์‹ธ์žˆ์ง€ ์•Š์œผ๋ฉด ํ•ด๋‹น ์ฃผ์†Œ๋ฅผ ๋งํ•œ๋‹ค.

Load & Store#

LDA, LDX, STA, STX, etc.

  • LDA m : A ๋ ˆ์ง€์Šคํ„ฐ โ† (m .. m+2), A ๋ ˆ์ง€์Šคํ„ฐ์— m ์ด ๊ฐ€๋ฅดํ‚ค๋Š” ๋ฉ”๋ชจ๋ฆฌ์ฃผ์†Œ์— ์žˆ๋Š” ๊ฐ’์„ Loadํ•จ.

  • LDX m : X ๋ ˆ์ง€์Šคํ„ฐ โ† (m .. m+2), X ๋ ˆ์ง€์Šคํ„ฐ์— m ์ด ๊ฐ€๋ฅดํ‚ค๋Š” ๋ฉ”๋ชจ๋ฆฌ์ฃผ์†Œ์— ์žˆ๋Š” ๊ฐ’์„ Loadํ•จ.

  • STA m : (m .. m+2) โ† A ๋ ˆ์ง€์Šคํ„ฐ, A ๋ ˆ์ง€์Šคํ„ฐ์— ์žˆ๋Š” ๊ฐ’์„ m ์ด ๊ฐ€๋ฅดํ‚ค๋Š” ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ์— Storeํ•จ.

  • STX m : (m .. m+2) โ† X ๋ ˆ์ง€์Šคํ„ฐ, X ๋ ˆ์ง€์Šคํ„ฐ์— ์žˆ๋Š” ๊ฐ’์„ m ์ด ๊ฐ€๋ฅดํ‚ค๋Š” ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ์— Storeํ•จ.

LDCH, STCH ์˜ Character ๋ฐ์ดํ„ฐ๋ฅผ ๋‹ค๋ฃฐ ๋•Œ๋Š” ์•ž์˜ 16๋น„ํŠธ๋ฅผ ์ž๋ฅด๊ณ  ๋งจ ๋’ค์˜ 8์ž๋ฆฌ๋งŒ Loadํ•˜๊ณ  Storeํ•œ๋‹ค

Arithmetic & Logic#

์ด ๋ช…๋ น์–ด๋“ค์€ ๋ชจ๋‘ A ๋ ˆ์ง€์Šคํ„ฐ์™€ ๊ด€๋ จ์ด ์žˆ๋‹ค.

  • ADD m : A โ† (A) + (m .. m+2)

  • SUB m : A โ† (A) - (m .. m+2)

  • MUL m : A โ† (A) * (m .. m+2)

  • DIV m : A โ† (A) / (m .. m+2)

  • AND m : A โ† (A) & (m .. m+2)

  • OR m : A โ† (A) | (m .. m+2)

Comparison#

2๊ฐ€์ง€ ๋ช…๋ น์–ด COMP ์™€ TIX

  • COMP m : ๋น„๊ต๋˜์–ด ๋‚˜์˜จ ๊ฐ’(ํฌ๋‹ค, ์ž‘๋‹ค, ๊ฐ™๋‹ค)์„ SW ๋ ˆ์ง€์Šคํ„ฐ์˜ Condition code์— ์ €์žฅํ•œ๋‹ค

  • TIX m : X โ† (X) + 1; ํ›„ X์™€ (m .. m+2) ๋ฅผ ๋น„๊ตํ•œ ๊ฒฐ๊ณผ๋ฅผ SW ๋ ˆ์ง€์Šคํ„ฐ์˜ Condition code์— ์ €์žฅํ•œ๋‹ค

Conditional Jumps#

SW ๋ ˆ์ง€์Šคํ„ฐ์˜ Condition code์— ๋”ฐ๋ผ ์ ํ”„ํ•˜๋Š” ๋ช…๋ น์–ด์ด๋‹ค.

J m : PC โ† (m .. m+2)

JLT m : PC โ† (m .. m+2) if CC set to <

JGT m : PC โ† (m .. m+2) if CC set to >

JEQ m : PC โ† (m .. m+2) if CC set to =

Subroutine Linkage#

JSUB m : L โ†(PC); PC โ† m

RSUB : PC โ† (L)

JSUB ์€ L(๋ง์ปค) ๋ฆฌํ„ด ํ•  ๋•Œ ๋Œ์•„๊ฐˆ ๊ฐ’์„ ๋ณด๊ด€ํ•˜๋Š” ๋ ˆ์ง€์Šคํ„ฐ์— PC๋ฅผ ์ €์žฅํ•ด๋‘๊ณ  PC ์— ์„œ๋ธŒ๋ฃจํ‹ด(m) ์„ ๋ถ€๋ฅธ๋‹ค. ๊ทธ๋ฆฌ๊ณ  m ์— ์žˆ๋Š” ๋ช…๋ น๋“ค์„ ์ˆ˜ํ–‰ํ•œ ํ›„, ๋‹ค์‹œ ์›๋ž˜์˜๋ฃจํ‹ด์œผ๋กœ L ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ์ฐธ์กฐํ•ด ๋Œ์•„์˜จ๋‹ค.

RSUB ์€ ๋ฆฌํ„ด๊ณผ ์œ ์‚ฌํ•œ ์˜๋ฏธ์ด๋‹ค.

I/O#

์ธํ’‹๊ณผ ์•„์›ƒํ’‹์€ ํ•œ๋ฒˆ์— 1๋ฐ”์ดํŠธ ์”ฉ๋งŒ ์ „์†กํ•œ๋‹ค. A ๋ ˆ์ง€์Šคํ„ฐ์˜ ๋งˆ์ง€๋ง‰ 1๋ฐ”์ดํŠธ (rightmost byte)๋ฅผ ์‚ฌ์šฉํ•œ๋‹ค. ๋ชจ๋“  ๋””๋ฐ”์ด์Šค๋Š” ๊ฐ๊ฐ์„ ๊ตฌ๋ณ„ํ•˜๊ธฐ ์œ„ํ•ด uniqueํ•œ 8๋น„ํŠธ์˜ ์ฝ”๋“œ๊ฐ€ ๋ถ€์—ฌ๋œ๋‹ค. ๋”ฐ๋ผ์„œ ๊ตฌ๋ณ„๋˜๋Š” ํ•œ๋„ ๋‚ด 2^8 ๊ฐœ์˜ ๋””๋ฐ”์ด์Šค๊ฐ€ ๋ถ™์„ ์ˆ˜ ์žˆ๋‹ค.

TD m : Test device specified by (m), (sets CC), < : device is ready, = device isn't ready

RD m : A[rightmost byte] โ† data from device specified by (m)

WD m : Device specified by (m) โ† (A)[rightmost byte]


SIC/XE Machine Architecture#

SIC/XE๋Š” SIC์˜ ์—…๊ทธ๋ ˆ์ด๋“œํŒ์œผ๋กœ ๋งŽ์€ ๊ธฐ๋Šฅ๋“ค์€ ๋™์ผํ•˜๋‹ค. ๋™์ผํ•œ ๋ถ€๋ถ„์„ ์ œ์™ธํ•˜๊ณ ๋ณ€ํ™”๋œ ๋ถ€๋ถ„์„ ์•Œ์•„๋ณธ๋‹ค.

๋ฉ”๋ชจ๋ฆฌ#

  • ์ „์ฒด ๋ฉ”๋ชจ๋ฆฌ๋Š” 1MB(2^20 ๋ฐ”์ดํŠธ)

๋ ˆ์ง€์Šคํ„ฐ#

SIC๊ฐ€ ๊ฐ€์ง„ 5๊ฐœ์˜ ๋ ˆ์ง€์Šคํ„ฐ์— ๋”ํ•ด 4๊ฐœ๊ฐ€ ๋” ์ถ”๊ฐ€๋˜์–ด 9๊ฐœ๊ฐ€ ๋˜์—ˆ๋‹ค. F ๋ ˆ์ง€์Šคํ„ฐ๋งŒ 48 ๋น„ํŠธ์ด๊ณ  ๋‚˜๋จธ์ง€๋Š” ๋ชจ๋‘ 24๋น„ํŠธ์ด๋‹ค.

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๋ฐ์ดํ„ฐ ํฌ๋งท#

48๋น„ํŠธ ๋ถ€๋™์†Œ์ˆ˜์ (Floating-point data type)์ด ์ถ”๊ฐ€๋˜์—ˆ๋‹ค. ์ด๊ฒƒ์€ ๋‹ค์Œ์˜ ํฌ๋งท์„๊ฐ€์ง„๋‹ค.

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๋ช…๋ น์–ด ํฌ๋งท#

SIC์™€๋Š” ๋‹ฌ๋ฆฌ ๋ช…๋ น์–ด๋ฅผ ์ฒ˜๋ฆฌํ•˜๋Š” ํฌ๋งท์ด ์กด์žฌํ•œ๋‹ค.

  • Format 1 (1 byte) : Opcode(8bits)

  • Format 2 (2 byte) : Opcode(8bits) + r1(4bits) + r2(4bits)

  • Format 3 (3 byte) (Flag e = 0) : Opcode(6bits) + | n | i | x | b | p | e | + address(12bits)

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  • Format 4 (4 byte) (Flag e = 1) : Opcode(6bits) + | n | i | x | b | p | e | + address(20bits)

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Addressing Modes#

  • Relative addressing modes for Format 3

    • Base relative addressing, when b=1, p=0 : TA = (B) + disp/addr

    • PC relative addressing, when b=0, p=1 : TA = (PC) + disp/addr

  • Direct addressing mode for Format 3 & 4

    • b = p = 0 : TA = disp/addr

when x=1 ์ผ ๋•Œ, indexed addressing์ด ๊ฒฐํ•ฉ๋˜์–ด (X)๊ฐ€ TA ๊ณ„์‚ฐ์— ๋”ํ•ด์ง„๋‹ค

  • i=1, n=0 : immediate addressing, ๋ฉ”๋ชจ๋ฆฌ ์ฐธ์กฐ ์—†์ด TA๊ฐ€ operand ๊ฐ’์œผ๋กœ ์“ฐ์ธ๋‹ค.

  • i=0, n=1 : indirect addressing, ๋ฉ”๋ชจ๋ฆฌ ์ฐธ์กฐ ๊ฐ’์œผ๋กœ ๋‹ค์‹œ ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ

indexed๋Š” immediate or indirect์—์„œ ์‚ฌ์šฉ๋  ์ˆ˜ ์—†๋‹ค.

  • i=0, n=0 : simple addressing for SIC

    • b, p, e ๊ฐ’์ด address field๋กœ ์“ฐ์ธ๋‹ค. (SIC์˜ address๋Š” 15bits์ด๋ฏ€๋กœ)
  • i=1, n=1 : simple addressing for SIC/XE

์ฐธ๊ณ ์ž๋ฃŒ#

SIC ๋จธ์‹ ์ด๋ž€? (๊ฐ€์ƒ ์ปดํ“จํ„ฐ)

SIC/XE ๋จธ์‹ ์ด๋ž€ ๋ฌด์—‡์ธ๊ฐ€?

SIC(Simplified Instructional Computer)์˜ ๊ตฌ์กฐ(Architecture), ๋ช…๋ น์–ด ํฌ๋ฉง(Instruction formats), ์ฃผ์†Œ ํ˜•์‹(Addressing modes)

SIC/XE์˜ ๊ตฌ์กฐ(Architecture), SIC๊ณผ ์–ด๋–ป๊ฒŒ ๋‹ค๋ฅธ๊ฐ€?, Special symbols